1. Field of the Invention
The present invention relates to the manufacturing method of array substrates for use in flat panel display devices including liquid crystal display (LCD) devices.
2. Description of the Related Art
In the recent years flat panel display devices are more frequently developed to replace conventional cathode-ray tube (CRT) units; in particular, LCD devices are becoming commercially attractive more and more due to their advantage such as light weight, thinness, low power consumption and the like.
As one typical prior known LCD devices, a light transmissive active-matrix LCD device will now be described herein which comes with a plurality of switch elements each of which is at a respective one of picture elements. The active-matrix LCD device includes a liquid crystal layer held between an array substrate and a counter substrate with orientation films being provided between the liquid crystal layer and any one of such substrates. The array substrate has, on a transparent insulative substrate made of glass, quartz or the like, a plurality of signal lines and a scanning lines arranged in a matrix form. At each of such crosspoints, a thin film transistor (abbreviated to xe2x80x9cTFTxe2x80x9d hereinafter) made of semiconductor thin film such as amorphous silicon (referred to as xe2x80x9ca-Si:Hxe2x80x9d) is connected to the lines. The TFT has a gate electrode electrically connected to a corresponding one of the scanning lines, a drain electrode electrically connected to a corresponding signal line, and a source electrode electrically connected to a transparent conductive material constituting an associated pixel electrode, which material may be indium-tin-oxide (ITO).
The counter substrate is constituted from a glass substrate on which an counter electrode made of ITO is disposed; where displaying of color images is required, a color filter layer will be additionally provided thereon.
With respect to the above-described active-matrix LCD device, construction of the array substrate will be further described by an example having TFTs equipped with channel protective films.
The scanning lines are formed of aluminum (Al) and anodic-oxidized coating layer, which coating layer is formed by anodic oxidation processing on surface layer of the Al in electrolytic solution. Storage capacitor lines are formed in the same manner.
Manufacturing method of these lines is as follows: firstly, an Al layer is deposited on a glass substrate by sputtering technique and then subjected to a patterning treatment to form a prescribed Al wiring pattern; then, certain region of the wiring pattern is selectively covered with anodic-oxidation-proof masking material such as resist, to leave certain Al pattern in the region intact; subsequently, by applying a prescribed voltage onto the Al pattern, an Al oxide layer is formed on the Al wiring pattern to prescribed thickness, for example to 200-300 nm. In this way, the scanning lines, gate electrodes and storage capacitor lines are formed. Subsequently, active portion of the TFT, the pixel electrode, the signal lines, and the source and drain electrodes are formed in a step-by-step manner, to complete the array substrate of the active-matrix LCD device.
However, because anodic-oxidized films have to cover the surface of the aluminum wiring that is a low-resistivity wiring, the manufacturing method requires an anodic oxidation processing including a mask-forming process, and requires extra wiring patterns for voltage supply for the anodic oxidation processes. Thus, a restriction arises in designing of gate wiring patterns, which are wiring patterns for scanning lines and gate electrodes. This restriction leads to lower productivity and lower freedom in designing.
In otherwise, there come to arise an idea of adopting wiring patterns solely made of aluminum. However, in this wiring pattern, deformation such as a hillock may occur. That is a phenomenon where portion of the wiring protrudes in thickness-wise direction. Forming of the hillock on the wiring leads to deterioration of interlayer dielectric property of dielectric films, remarkably decreasing production yield of the array substrate.
Moreover, there has been a problem in that, at an etching process for forming pixel electrodes, its etchant penetrates into the Al wiring layer to corrode the Al, so as to lower the production yield.
The invention aims to secure low-resistivity of the wiring and yet effectively prevent interlayer short-circuit caused by the deformation of the wiring. The invention also aims to prevent corrosion of the wiring metal layer during the etching process, and thereby prevent decrease of production yield.
The invention according to claim 1 provides a method of manufacturing an array substrate for a display device having a scanning line and gate electrode on a substrate; a thin film transistor having a gate insulator film on said scanning line and gate electrode, a semiconductor film thereon, source and drain electrodes electrically connected to said semiconductor film; a signal line as taken out of the drain electrode to extend substantially perpendicularly to said scanning line; and a pixel electrode electrically connected to the source electrode, comprising steps of: forming said scanning line and gate electrode by patterning a multi-layer metal film having an aluminum alloy layer and a refractory metal layer; and depositing said gate insulator film in direct contact with said scanning line and gate electrode at a temperature not less than 300xc2x0 C.
The above construction of the scanning line is exemplified as follows. As an Al alloy, an aluminum-neodymium alloy (Alxe2x80x94Nd) of 2 atomic % neodymium is deposited in 300 nm thickness. Then, a refractory metal is deposited on the Al alloy. Thus formed multi-layer film is subjected to a taper-shape-forming processing to form scanning lines. Subsequently, a gate insulator film is formed by plasma CVD techniques at substrate temperature of 350xc2x0 C.
Due to this multi-layer formation by an Al alloy layer and a refractory metal layer, no deformation of the Al layer and no failure of the dielectric film take place without causing decrease in the production yield of the array substrates. Thus, a wiring resistivity same or lower than that of prior art can be accomplished without causing decrease in the production yield.
At a process step for forming said pixel electrode, even when an etching process is carried out by hydrobromic acid (HBrxe2x80xa2aq), hydroiodic acid (HIxe2x80xa2aq), oxalic acid ((COOH)2) or a mixture liquid containing at least one of these acid, or even when a dry-etching process is carried out, the Al alloy undergoes no damage from such etching agents because the refractory metal and the gate insulator film are disposed between the etching agents and the scanning line comprised of Al alloy.